Integrated circuit and sensor industries are focused on minimization of component dimensions. However, because of small signals produced by continuously smaller designed devices, processing of the electronic signals produced by small discrete devices has proved to be a complicated matter. Since signals from a discrete sensor must be sufficiently large and robust to be passed to its compensating electronics, which is often situated on another chip, undesirable compromises in the sensor, including larger sensing element size, larger chip sizes and lower multiples per wafer, often must be made to sufficiently increase the signal strength of the discrete sensor.
Because of the small electronic signals produced by a small discrete sensor, and the existing desire for a smaller sensor element, the discrete sensor must be situated in close proximity to the compensating electronics. This constraint currently requires that the compensating electronics chip be in the same package as the discrete sensor. For a discrete sensor to communicate with a compensator chip, the two chips must be electrically connected. This typically involves wire bonds between the chips. However, there are electrical problems with manipulating small signals, including stray capacitances due to these chip-to-chip wire bonds. Thus, contemporary packaging approaches are limited since these small signals must be protected. As an example, since the sensor element is moveable, the wire bonds may not be gelled in place in the package. This allows the wire bonds to move relative to each other, which can modulate the capacitance between the wires, thus distorting the signals between the sensor and the compensator chip. Thus, it is important to integrate the compensating electronics on the same chip as the sensor element, resulting in a need to isolate portions of an epitaxial silicon layer from each other.
Contemporary devices typically include discrete sensor chips and corresponding electrical compensating chips, usually made in a CMOS (complementary metal-on-oxide) process. Typical CMOS processes do not use isolation schemes that reach the depths typical of a silicon-on-insulator (SOI) substrate whose epitaxial layer is sufficiently thick to form a sensor element. Thus, combining a standard CMOS process with a sensor process in order to realize an integrated sensor requires an isolation scheme capable of isolating the entire thickness of the epitaxial layer. Adding such an isolation scheme to the established CMOS process requires significant modification of the CMOS process, adding risk and process complexity to the CMOS. Since it is unlikely that CMOS foundries will agree to incorporate necessary isolation steps into their standard processes, the sources of CMOS are limited.
Junction isolation is one contemporary isolation method that may be used in a CMOS process. Junction isolation is not a feasible isolation scheme for an integrated sensor because of its prohibitively excessive area, due to the isotropic nature of the dopant profile once it has been diffused completely through the epitaxial silicon layer. Typically, an all-silicon sensor element requires a relatively thick epitaxial layer, about 20-40 micrometers in one example. Thus, the lateral diffusion from the junction diffusion is also large. Further, sensor devices are sensitive to the junction capacitances that a junction isolation scheme would introduce into a device.
Trench and fill is another common contemporary isolation scheme often employed in an integrated sensor process. This scheme typically employs a high aspect ratio trench, which can be difficult to achieve. The isolation trench requires particular sidewall profiles including no re-entrant trench wall angles or bow at the top of the trench. It may also be advantageous to construct a slightly V-shaped trench, but the trench bottom must not be pinched off prior to terminating on the underlying oxide layer. Isolation trenches, once etched, typically require a liner oxide prior to the applying a trench fill material. The liner oxide is typically a thermal oxide. If the liner oxide layer is too thick, the oxidation creates damage to the silicon, causing dislocations and slip, which may extend into device areas and cause electrical leakage. Additionally, thermal cycles required to form the oxide trench liner increase the thermal budget of the CMOS process, become a process proliferation expense to the wafer fabrication facility, and add cycle time to the process
The fill material for the trench requires a coefficient of thermal expansion match with silicon. Typically, polysilicon is used as a trench fill material, since it has a similar thermal expansion to silicon. However, polysilicon is conformal, and if there is a bow in the top of the trench, there will be a keyhole formed within the polysilicon near the top of the trench. Also, the thickness of the polysilicon needed to fill the trench must be at least equal to one-half the trench width, and often nearly equal to the width of the trench. This is often larger than the polysilicon thicknesses (typically 2000-3500 A) used in a typical CMOS process. A typical isolation trench width is 1.5-2 microns, which requires a polysilicon thickness for a trench fill of 1.5-4 microns of polysilicon, which is a factor of 4-10 more than a typical CMOS process polysilicon thickness. This decreases the operation availability of the polysilicon deposition tube due to both the thick polysilicon layer deposition cycle time and the increased polysilicon tube cleaning frequency.
Once the polysilicon is deposited, it must be etched back leaving the polysilicon preferentially in the trench, but removed from the top surface of the wafer allowing further processing of the CMOS. The etch back is not a trivial step, and can expose a keyhole in the center of the fill, particularly if the fill material is a conformal material, and the trench is re-entrant or has a bow in the top. Such exposed keyholes can become contamination sources. It can be difficult to remove conductive material such as successive polysilicon layers and metal layers from keyholes, possibly leading to contamination, stringers and shorts. Methods to eliminate keyholes, including making champagne glass-shaped trench tops, add process expense and complexity, and may also lead to silicon stringers and thus shorts around the isolation trench. Usually after the polysilicon is etched back, it requires passivation. Typically the polysilicon is capped with a dielectric film. This requires a deposition or a thermal oxidation step. With thermal oxidation, a vertical bird's beak may damage the silicon crystallinity at the top of the trench. Also, any capping method requires additional processing.
Trench fill material other than polysilicon may be used, all having idiosyncratic difficulties. Spin-on glasses (SOG) fail to repetitively fill trenches, and can crack, particularly when the layers are thick, and typically require thermal densification to drive off solvents and cure the film. Chemical vapor deposition (CVD) films, including low pressure CVD (LPCVD), plasma enhanced CVD (PECVD) and others (inorganics) may tend to have poor conformity, and “breadloaf” when deposited over steps, which lead to incompletely filled trenches. Further, CVD deposited films, used as a trench fill material, tend to leave a seam down the center of the trench. This may crack the conductor lines running on top of them. Highly doped glasses (LTO and TEOS) are contamination risks, cannot be accomplished early in the CMOS process, and tend not to be conformal, requiring a reflow step. CVD films other than polysilicon, such as silicon nitride, suffer from the same problems and are limited in thickness. Standard CVD recipes may also require modification to provide low stress films. Low stress films tend to demand more deposition tube maintenance than standard CVD film recipes.
Typical SOI based sensor element formation requires removal of a sacrificial oxide film to release the element. This oxide is usually removed with a wet etch, a combination wet and dry etch, or a dry etch. A wet etch suffers from stiction between the moving element and the surfaces surrounding the moving element. Combination wet and dry release methods require additional masks and process steps. Dry oxide removal processes, like vapor HF, require expensive equipment and must incorporate methods for protecting the other standard semiconductor films used on the device from the dry etchant chemical.